Method of fabricating transistors with low thermal budget
US6399452B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2000 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Jul 8, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A low thermal budget transistor is fabricated by first forming a gate on a semiconductor substrate. First amorphous regions and first inactive dopant regions are then created in the substrate by ion implantation. Sidewall spacers, which align subsequent implantation steps, are formed adjacent to the gate. Thereafter, second amorphous regions and second inactive dopant regions are created in the substrate by ion implantation. Dopants in the first and second inactive dopant regions are then activated using a low temperature annealing process to create source/drain regions and source/drain extension regions. The aforementioned process simplifies the fabrication of a low thermal budget transistor by dispensing with the requirement to remove the sidewall spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.