Stacked structure of semiconductor means and method for manufacturing the same
US6400007B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2001 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Apr 16, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An stacked structure of semiconductor means and method for manufacturing the same, comprises a substrate, a lower semiconductor chip, an adhered glue layer, a plurality of wires and an upper semiconductor chip. The adhered glue layer located between the substrate and the lower semiconductor to adhere the lower semiconductor to the substrate. The overflow glue of the adhered glue layer covered above the periphery of the lower semiconductor chip. The plurality of wires each being electrically connected to the lower semiconductor chip and the substrate, so that each wires are located above the overflow glue. The upper semiconductor chip is located above lower semiconductor chip and electrically connected to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.