Flip-chip package structure and method of fabricating the same
US6400036B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2001 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Aug 1, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A flip-chip package technology is proposed for use to fabricate a dual-chip integrated circuit package that includes two semiconductor chips in a single package unit, which is characterized in the forming of a flash-barrier structure that can help prevent the underfill material used in flip-chip underfill process from flashing to other unintended areas. The flash-barrier structure can be either a protruded dam structure over the underlying semiconductor chip, or a groove in a coating layer formed over the underlying semiconductor chip. During flip-chip underfill process, the flash-barrier structure can confine the underfill material within the intended area and prevent the underfill material from flowing to other unintended areas such as nearby bonding pads, so that the finished package product can be assured in quality and reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.