Apparatus for and method of detecting a delay fault in a phase-locked loop circuit
US6400129B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2000 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Jan 28, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R25/00
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
There is provided a method and an apparatus for detecting a delay fault in a phase-locked loop circuit. A frequency impulse is applied to the PLL circuit under test as a reference clock, and a waveform of a signal outputted from the PLL circuit under test is transformed to an analytic signal to estimate its instantaneous phase. A linear phase is estimated from the estimated instantaneous phase, and the estimated linear phase is removed from the estimated instantaneous phase to obtain a fluctuation term of the instantaneous phase. A delay fault is detected by comparing a time duration during which the PLL circuit stays in a state of oscillating a certain frequency with the time duration during which a fault-free PLL circuit stays in a state of oscillating a certain frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.