Rapid execution of floating point load control word instructions
US6405305B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 1999 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Sep 10, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor with a floating point unit configured to rapidly execute floating point load control word (FLDCW) type instructions in an out of program order context is disclosed. The floating point unit is configured to schedule instructions older than the FLDCW-type instruction before the FLDCW-type instruction is scheduled. The FLDCW-type instruction acts as a barrier to prevent instructions occurring after the FLDCW-type instruction in program order from executing before the FLDCW-type instruction. Indicator bits may be used to simplify instruction scheduling, and copies of the floating point control word may be stored for instruction that have long execution cycles. A method and computer configured to rapidly execute FLDCW-type instructions in an out of program order context are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.