High K dielectric de-coupling capacitor embedded in backend interconnect
US6417556B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2000 |
| Grant date | Jul 9, 2002 |
| Priority date | — |
| Expiry date | Feb 2, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) including an integral, high k dielectric de-coupling capacitor constructed using a single conductive layer within the IC structure. The IC comprises a substrate, a dielectric layer disposed over the substrate, and a conductive layer disposed over the dielectric layer. The conductive layer includes a first line disposed adjacent to a second line, and a high k dielectric material disposed between the first line and the second line. The capacitor is formed between the first line and the second line separated by the high k dielectric material. The capacitor is connected by coupling the first line to a signal and coupling the second line to a capacitor signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.