Hardmask trim process
US6420097B1 · kind B1 · utility
33Cited by
13References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 2, 2000 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | May 2, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28123
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved method of forming circuit structures having linewidths which are smaller than what is achievable by conventional UV lithographic techniques on ultra-thin resist layers is provided. The method includes a hardmask which is patterned using an ultra-thin resist layer and is then trimmed to reduce the width of the hardmask before etching the underlying gate conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.