Method of forming a silicide region in a Si substrate and a device having same
US6420264B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2001 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Jun 28, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a silicide region (80) on a Si substrate (10) in the manufacturing of semiconductor integrated devices, a method of forming a semiconductor device (MISFET), and a device having suicide regions formed by the present method. The method of forming a suicide region involves forming a silicide region (80) in the (crystalline) Si substrate having an upper surface (12) and a lower surface (14). The method comprises the steps of first forming an amorphous doped region (40) in the Si substrate at or near the upper surface, to a predetermined depth (d). This results in the formation of an amorphous-crystalline interface (I) between the amorphous doped region and the crystalline Si substrate. The next step is forming a metal layer (60) atop the Si substrate upper surface, in contact with the amorphous doped region. The next step involves performing backside irradiation with a first radiation beam (66). This heats the interface sufficient to initiate explosive recrystallization (XRC) of amorphous doped region. This, in turn, provides heat to the metal layer sufficient to cause the diffusion of metal atoms from the metal layer into the amorphous doped region. In this manner,…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.