Method for forming an integrated barrier/plug for a stacked capacitor
US6420267B1 · kind B1 · utility
3Cited by
2References
8Claims
0Family size
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Key dates
| Filing date | Apr 18, 2000 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Apr 18, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an integrated barrier/contact for stacked capacitors is provided which results in reduced cost of ownership and in a barrier which is nominally several times thicker than convention structures. The resulting structure results in decreased contact plug resistance as compared with conventional devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.