LDMOS power device with oversized dwell
US6424005B1 · kind B1 · utility
94Cited by
9References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 3, 1998 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | Dec 3, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
An LDMOS device (10, 20, 50, 60) that is made with minimal feature size fabrication methods, but overcomes potential problems of misaligned Dwells (13). The Dwell (13) is slightly overstated so that its n-type dopant is implanted past the source edge of the gate region (18), which permits the n-type region of the Dwell to diffuse under the gate region (18) an sufficient distance to eliminate misalignment effects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.