Method and apparatus for rapid execution of FCOM and FSTSW
US6425074B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 1999 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | Sep 10, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/38585
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor configured to rapidly execute floating point store status word (FSTSW) type instructions that are immediately preceded by floating point compare (FCOM) type instructions is disclosed. FCOM-type instructions are modified to store their results to an architectural floating point status word and a temporary destination register. If an FSTSW-type instruction is detected immediately following an FCOM-type instruction, then the FSTSW-type instruction is transformed into a special fast floating point store status word (FSTSWEF) instruction. Unlike the FSTSW-type instruction, which is serializing and negatively impacts performance, the FSTSWEF instruction is not serializing and allows execution to continue without undue serialization. A computer system and method for rapidly executing FSTSW instructions immediately preceded by FCOM-type instructions are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.