Removable spacer technology using ion implantation to augment etch rate differences of spacer materials

US6429083B1 · kind B1 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Emi Ishida · Sunnyvale, US
• Srinath Krishnan · Campbell, US
• Ming-Yin Hao · Nanjing, CN
• Effiong Ibok · Sunnyvale, US

Key dates

• Filing date: Jun 21, 2000
• Grant date: Aug 6, 2002
• Expiry date: Jun 21, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/021

Abstract

Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which has been treated subsequent to its deposition, e.g., by ion implantation, to augment its etch rate with a room temperature etchant, e.g., dilute aqueous HF. The treated spacers are removed with the dilute, aqueous HF after implantation of moderately or heavily-doped source/drain regions but prior to any post-implantation annealing processing, in order not to increase the etch resistance of the spacer material by thermally-induced densification.