Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate
US6429109B1 · kind B1 · utility
10Cited by
5References
35Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2001 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Dec 14, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a gate comprising the following steps. A substrate is provided. A pre-gate structure is formed over the substrate. The pregate structure includes a sacrificial metal layer between an upper gate conductor layer and a lower gate dielectric layer. The pre-gate structure is annealed to form the gate. The gate comprising: an upper silicide layer formed from a portion of the sacrificial metal layer and a portion of the upper gate conductor layer from the anneal; and a lower metal oxide layer formed from a portion of the gate dielectric layer and a portion of the sacrificial metal layer from the anneal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.