Optical Proximity Correction Structures Having Decoupling Capacitors

US6429469B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Archibald J. Allen · Shelburne, US
• Orest Bula · Shelburne, US
• John M. Cohn · South Burlington, US
• Daniel C. Cole · Jericho, US
• Edward W. Conrad · Jeffersonville, US
• William C. Leipold · Enosburg Falls, US

Key dates

• Filing date: Nov 2, 2000
• Grant date: Aug 6, 2002
• Expiry date: Nov 2, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/811

Abstract

A structure for a semiconductor chip which includes a first region having first cells for storing and processing data, and a second region outside the first region having OPC structures, wherein the OPC structures comprise decoupling capacitors. The line widths of the active gates of first cells are the same size or similar in size as the OPC structures. The OPC structures reduce proximity effects of active devices in the first cells, and comprise N-type FETs and P-type FETs, that are located in the second region. The OPC structures may have a width greater than the first cells. The second region can be multiple OPC structures, whereby the second region comprises multiple decoupling capacitors. The active devices in the first cells are separated by a first distance and the OPC structures are separated from the active devices by the first distance.