Double SOI device with recess etch and epitaxy

US6432754B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Fariborz Assaderaghi · Jefferson Valley, US
• Tze-Chiang Chen · Yorktown Heights, US
• K. Paul Muller · Wappingers Falls, US
• Edward J. Nowak · South Burlington, US
• Devendra K. Sadana · Pleasantville, US
• Ghavam G. Shahidi · Pound Ridge, US

Key dates

• Filing date: Feb 20, 2001
• Grant date: Aug 13, 2002
• Expiry date: Feb 20, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6758

Abstract

The present invention provides various methods for forming a ground-plane SOI device which comprises at least a field effect transistor formed on a top Si-containing surface of a silicon-on-insulator (SOI) wafer; and an oxide region present beneath the field effect transistor, located in an area between source and drain regions which are formed in said SOI wafer, said oxide region is butted against shallow extensions formed in said SOI wafer, and is laterally adjacent to said source and drain regions.