ILD planarization method
US6432827B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2000 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Nov 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method of planarization for an inter layer dielectric of an EDRAM. The method comprises defining a periphery circuit region and a memory array area on a semiconductor wafer of the EDRAM, and forming a plurality of MOS transistors and capacitors. As well, both a dielectric layer and a photoresist layer are formed on the semiconductor wafer using the layout patterns of a storage node of thecapacitors as a reverse mask to perform an etching process. Consequently, portions of the photoresist layer in the memory array area are removed while simultaneously etching the dielectric layer in the memory array area by a predetermined depth. Finally, a chemical mechanical polishing process is performed on the dielectric layer to planarize the inter layer dielectric of the EDRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.