Calibration technique for memory devices
US6434081B1 · kind B1 · utility
161Cited by
14References
104Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 12, 2000 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | May 12, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an improved start-up/reset calibration apparatus and method for use in a memory device One of a plurality of data paths is bit wise calibrated relative to a clock signal and thereafter others of the plurality of data paths are bit wise aligned to a previously calibrated data path to produce serial and parallel bit alignment on all data paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.