Process for fabricating a self-aligned double-polysilicon bipolar transistor

US6436782B2 · kind B2 · utility

Assignee

• STMicroelectronics SA

Inventors

• Alain Chantre · Seyssinet-Pariset, FR
• Michel Marty · Buc, FR
• Helene Baudry · Grenoble, FR

Key dates

• Filing date: Feb 28, 2001
• Grant date: Aug 20, 2002
• Expiry date: Feb 28, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D10/021

Abstract

The process includes successively forming, over a base region of a semiconductor substrate, a poly-Ge or poly-SiGe layer, an etch-stop layer over a selected zone of the Ge or SiGe layer, a layer of poly-Si of the same conductivity type as the base region, then an outer layer of dielectric material. Etching the layers includes stopping at the stop layer to form an emitter window preform, removing the stop film and selectively removing the Ge or SiGe layer in the emitter window preform to form an emitter window and to form an emitter made of poly-Si of conductivity type the opposite of the base region in the window.