Semiconductor-on-insulator transistor with recessed source and drain
US6437404B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2000 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Aug 10, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28079
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fully-depleted semiconductor-on-insulator (SOI) transistor device has an SOI substrate with a buried insulator layer having a nonuniform depth relative to a top surface of the substrate, the buried insulator layer having a shallow portion closer to the top surface than deep portions of the layer. A gate is formed on a thin semiconductor layer between the top surface and the shallow portion of the insulator layer. Source and drain regions are formed on either side of the gate, the source and drain regions each being atop one of the deep portions of the buried insulator layer. The source and drain regions thereby have a greater thickness than the thin semiconductor layer. Thick silicide regions formed in the source and drain regions have low parasitic resistance. A method of making the transistor device includes forming a dummy gate structure on an SOI substrate, and using the dummy gate structure to control the depth of an implantation to form the nonuniform depth buried insulator layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.