Threshold voltage compacting for non-volatile semiconductor memory designs
US6438037B1 · kind B1 · utility
36Cited by
3References
10Claims
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Key dates
| Filing date | May 9, 2001 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | May 9, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory design with a compact threshold voltage distribution and a method for compacting the threshold voltage for a flash memory design in which the threshold voltage is compacted by erasing a plurality of memory cells to set the threshold voltage for the memory cells substantially towards a median erased threshold voltage; verifying at least one fast-erase memory cell; selectively soft-programming the memory cells; and erasing subsequent to selectively soft-programming.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.