Adjustable I/O timing from externally applied voltage
US6438043B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1998 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Sep 2, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4239
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit, including but not limited to a memory device, receives an externally provided voltage signal and selectively adjusts the timing of internal control signals. An external signal selects between two possible pre-determined delay paths. The delay paths are adjusted using fuse circuitry which can be programmed by the manufacturer prior to implementation by a user. The delay path adjustment feature is particularly applicable to adjusting output signal timing to allow the integrated circuit to be operated in an environment which requires slower communications speeds. The same integrated circuit, therefore, can also be implemented in an environment which allows for faster communications speeds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.