Timesharing internal bus, particularly for non-volatile memories
US6438669B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 1997 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Mar 7, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device that comprises an internal bus for the transmission of data and other information of the memory to output pads; a timer; and an enabling/disabling circuit for enabling and disabling access to the internal bus; the timer controlling the internal bus to transmit information signals of the memory device that originate from local auxiliary lines over the internal bus when the bus is in an inactive period during a normal memory data reading cycle; the timer controlling the enabling/disabling means to allow/deny access to the internal bus on the part of the information signals or of the data from or to the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.