Photoresist spacer process simplification to eliminate the standard polysilicon or oxide spacer process for flash memory circuits
US6440789B1 · kind B1 · utility
2Cited by
4References
3Claims
0Family size
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Key dates
| Filing date | Nov 1, 2000 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Nov 1, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A method of manufacturing a flash memory semiconductor device that eliminates the step of forming sidewall spacers on n-channel and p-channel transistor gate structures. Resist spacers having a dimension of Gn+2Sn are formed on n-channel transistor gate structures and an N+ implant is performed to form N+ implant is performed to form N+ regions in the n-channel substrate region. Resist spacers having a dimension of Gs +2Sp are formed on p-channel transistor gate structures and a P+ implant is performed to form P+ regions in the p-channel substrate region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.