Tailored erase method using higher program VT and higher negative gate erase
US6442074B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2001 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Feb 28, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for programming and erasing the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT and an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. After the first erase pulse, the erase verify routine is performed on all the IO's together. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. This erase pulse that provides a substantially high electric field is selected to erase band to band currents for the entire array that are larger than can be supplied by drain pumps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.