Patent · US Expired

Method for operating an integrated memory

US6445607B2 · kind B2 · utility

0Cited by

4References

3Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Robert Esterl
Heinz Honigschmid · Starnberg, DE
Helmut Kandolf · Hersbruck, DE
Thomas Rohr · Aschheim, DE

Key dates

Filing date	Apr 9, 2001
Grant date	Sep 3, 2002
Priority date	—
Expiry date	Apr 9, 2021

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/22
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A description is given of a method for operating an integrated memory which has memory cells each having a selection transistor and a storage capacitor with a ferroelectric storage effect. The memory contains a plate line, which is connected to one of the column lines via a series circuit containing a selection transistor and a storage capacitor of respective memory cells. A memory access is carried out according to the “pulsed plate concept”. In this case, the temporal sequence is controlled in such a way that, in an access cycle, the storage capacitor of the memory cell to be selected is in each case charged and discharged by the same amount. An attenuation or destruction of the information stored in the memory cells, which is caused by source-drain leakage currents of unactivated selection transistors, is thus avoided.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.