Address dependent caching behavior within a data processing system having HSA (hashed storage architecture)
US6446165B1 · kind B1 · utility
3Cited by
38References
23Claims
0Family size
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Key dates
| Filing date | Jul 30, 1999 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Jul 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of caches at a same level. The caches, which store data utilized by the execution unit, each store only data having associated addresses within a respective one of a plurality of subsets of an address space and implement diverse caching behaviors. The diverse caching behaviors can include differing memory update policies, differing coherence protocols, differing prefetch behaviors, and differing cache line replacement policies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.