Semiconductor with increased gate coupling coefficient
US6448606B1 · kind B1 · utility
34Cited by
9References
12Claims
0Family size
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Key dates
| Filing date | Feb 24, 2000 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Feb 24, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6891
Abstract
A reduced device geometry semiconductor memory device is provided which has increased device efficiency because of an increased gate coupling coefficient. Shallow trench isolations are formed in a semiconductor substrate. The shallow trench isolations are selectively shaped in order to form a control gate dielectric layer later with a large width relative to the width between the floating gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.