Asymmetrical cache properties within a hashed storage subsystem
US6449691B1 · kind B1 · utility
1Cited by
38References
21Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 30, 1999 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Jul 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of caches at a same level. The caches, which store data utilized by the execution unit, have diverse cache hardware and each preferably store only data having associated addresses within a respective one of a plurality of subsets of an address space. The diverse cache hardware can include, for example, differing cache sizes, differing associativities, differing sectoring, and differing inclusivities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.