Method of forming low-leakage on-chip capacitor
US6451662B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2001 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Oct 4, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved capacitor is formed by a process where an improved node dielectric layer is formed with an improved dielectric constant by performing an Free Radical Enhanced Rapid Thermal Oxidation (FRE RTO) step during formation of the node dielectric layer. Use of an FRE RTO step instead of the conventional furnace oxidation step produces a cleaner oxide with a higher dielectric constant and higher capacitance. Other specific embodiments of the invention include improved node dielectric layer by one or more additional nitridation steps, done by either Remote Plasma Nitridation (RPN), Rapid Thermal Nitridation (RTN), Decoupled Plasma Nitridation (DPN) or other nitridation method; selective oxidation; use of a metal layer rather than a SiN layer as the dielectric base; and selective oxidation of the metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.