Intermetal dielectric layer for integrated circuits
US6451687B1 · kind B1 · utility
10Cited by
9References
10Claims
0Family size
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Key dates
| Filing date | Nov 24, 2000 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Nov 24, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02274
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An intermetal dielectric structure for integrated circuits and a manufacturing method therefore is provided having a premetal dielectric and a metal line thereon, with a SRO liner on the premetal dielectric layer and the metal lines, a FGS dielectric layer over the SRO liner, a SRO film over the FGS dielectric layer, and a TEOS dielectric layer over the SRO film. Vias through the FGS dielectric layer are treated to have fluorine-free regions around the vias. The structure is not subject to fluorine attack on the metal lines or vias while having a stable FGS dielectric layer with less fluorine out-gassing and out-diffusion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.