Method and system for performing transition fault simulation along long circuit paths for high-quality automatic test pattern generation
US6453437B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 1999 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Jul 1, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318342
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for generating a test pattern for use in testing an integrated circuit device. The computer implemented steps of receiving and storing the netlist specification in a computer memory unit, and simulating the netlist using the computer implemented synthesis system. Using the netlist simulation, a set of circuit paths for each fault of the plurality of faults within the netlist specification is determined. From this set of paths, respective longest paths for each fault is determined. Using an ATPG (automatic test pattern generation) process, a test vector is determined for the first fault. Transition fault simulation is then performed on the first fault by applying the test vector to a first path through the first fault, wherein the first path is the longest path traversing through the first fault as determined by the ATPG process. Responsive to the transition fault simulation, a second fault that is fortuitously detected by the test vector as applied to a second path traversing through the second fault is identified. The test vector is credited with detecting the first fault, and, provided the second path is the longest path that traverses through the second fault, the test …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.