Semiconductor fabrication with multiple low dose implant
US6455385B1 · kind B1 · utility
11Cited by
12References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 7, 1998 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Jan 7, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of reducing implant dose loss is provided. The method includes performing multiple low dose implant steps with interspersed anneal steps, thereby avoiding amorphous-silicon formation. The anneal steps may be performed at high temperatures or at low temperatures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.