Method of drain avalanche programming of a non-volatile memory cell
US6456531B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2001 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Jun 19, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of programming a memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes applying a constant first voltage across the gate, applying a second constant voltage across the first region, and applying a third constant voltage across the second region that is near the avalanche breakdown voltage of the second region so that spillover electrons are significantly reduced in number within the channel when compared to if the third constant voltage is well below the avalanche breakdown voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.