Process for manufacturing semiconductor integrated circuit device
US6458674B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2002 |
| Grant date | Oct 1, 2002 |
| Priority date | — |
| Expiry date | Jan 18, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/906
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the resurfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.