Patent · US Expired

Integrated memory having memory cells and reference cells, and corresponding operating method

US6459626B1 · kind B1 · utility

2Cited by

7References

5Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Thomas Böhm · Zorneding, DE
Georg Braun · Hersbruck, DE
Heinz Honigschmid · Starnberg, DE
Zoltan Manyoki · Gatineau, CA
Thomas Rohr · Aschheim, DE

Key dates

Filing date	Sep 24, 2001
Grant date	Oct 1, 2002
Priority date	—
Expiry date	Sep 24, 2021

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/22
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated memory has two first switching elements, which respectively connect a bit line of a first bit line pair to a bit line of a second bit line pair. In addition, the integrated memory has two second switching elements, which respectively connect one of the reference cells of one bit line pair to that bit line of the other bit line pair which is not connected via the corresponding first switching element to the bit line assigned to this reference cell. Information is written back to the reference cells via the sense amplifiers. A method of operating the integrated memory is also provided.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.