Flip-chip with matched lines and ground plane
US6462423B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2000 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | Sep 6, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for substantially reducing the need for capacitive and inductive compensation for signal lines on a flip-chip semiconductor device. A flip-chip semiconductor device is disclosed having signal lines of substantially equal length. At least one ground plane is also disposed on the flip-chip device and separated from the signal lines by a dielectric layer. By using a ground plane and signal lines having substantially equal lengths, impedance caused by electromagnetic and electromagnetic coupling is significantly reduced, and impedance from signal line length is balanced such that the load on each of the signal lines, as viewed by the semiconductor die, are substantially equal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.