Method of fabricating CMOS device with dual gate electrode
US6468851B1 · kind B1 · utility
24Cited by
9References
39Claims
0Family size
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Key dates
| Filing date | Jan 2, 2002 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | Jan 2, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0177
Abstract
A method of fabricating a dual gate electrode CMOS device having dual gate electrodes. An N+ poly gate is used for the nMOSFET and a metal gate is used for the pMOSFET. The N+ nMOSFET poly gate may be capped with a highly conductive metal to reduce its gate resistance. A sacrificial cap is used for the N+ poly gate to eliminate a mask level for the dual gate electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.