Passivation of copper interconnect surfaces with a passivating metal layer

US6468906B1 · kind B1 · utility

Assignees

• Chartered Semiconductor Manufacturing LTD · SG
• NATIONAL UNIVERSITY OF SINGAPORE · SG
• Namyang Technological University of Singapore · SG
• Institute of Microelectronics · SG

Inventors

• Lap Chan · San Francisco, US
• Kuan Pei Yap · Kapar, MY
• Kheng Chok Tee · Singapore, SG
• Flora S. Ip · Singapore, SG
• Wye Boon Loh · Kluang, MY

Key dates

• Filing date: Jul 14, 2000
• Grant date: Oct 22, 2002
• Expiry date: Jul 14, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76886
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An interconnect line on an IMD layer on a semiconductor device is formed in an interconnect hole in the IMD layer. The interconnect hole has walls and a bottom in the IMD layer. A diffusion barrier is formed on the walls and the bottom of the hole. Fill the interconnect hole with a copper metal line. Perform a CMP step to planarize the device and to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole. Alternatively, a blanket deposit of a copper metal line layer covers the diffusion layer and fills the interconnect hole with a copper metal line. Perform a CMP process to planarize the device to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole in a self-aligned deposition process.