MOS transistor processing utilizing UV-nitride removable spacer and HF etch
US6472283B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2000 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Sep 22, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
Abstract
Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which is readily etched in its as-deposited, undensified state but difficult-to-etch in its thermally annealed, densified state. The as-deposited, undensified spacers are removed by etching with dilute aqueous HF after implantation of moderately or heavily-doped source/drain regions but prior to annealing of the implants for dopant diffusion/activation and lattice damage relaxation. Lightly- or moderately doped, shallow-depth source/drain extensions are implanted and annealed after spacer removal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.