Semiconductor package including stacked semiconductor dies and bond wires
US6472758B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2000 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Jul 20, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/21
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention provides a method for making a semiconductor package with stacked dies that eliminates fracturing of the upper die(s) during the wire bonding process. One embodiment of the method includes the provision of a substrate and pair of semiconductor dies, each having opposite top and bottom surfaces and a plurality of wire bonding pads around the peripheries of their respective top surfaces. One die is attached and wire bonded to a top surface of the substrate. A measured quantity of an uncured, fluid adhesive is dispensed onto the top surface of the first die, and the adhesive is squeezed toward the edges of the dies by pressing the bottom surface of the second die down onto the adhesive until the two dies are separated by a layer of the adhesive. The adhesive is cured, the second die is then wire bonded to the substrate, and the dies are then molded over with an encapsulant. The layer of adhesive prevents the second die from shorting the wires on the top of the first die, prevents the second die from being fractured during the wire bonding process, and prevents the encapsulant from forming a thermally expansive wedge between the two dies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.