Damascene NiSi metal gate high-k transistor
US6475874B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2000 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Jan 29, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying low temperature silicidation metal to interact to form the self-aligned low temperature metal silicide gate. A precursor having a temporary gate is used to form the self-aligned low temperature silicide gate. The remaining portions of the low temperature silicidation metal is removed by manipulating the etch selectivity between the low temperature silicidation metal and the self-aligned low temperature metal silicide gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.