Dielectric treatment in integrated circuit interconnects
US6479898B1 · kind B1 · utility
5Cited by
7References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2001 |
| Grant date | Nov 12, 2002 |
| Priority date | — |
| Expiry date | Jan 11, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein and a surface region of nitrogen. A barrier layer lines the channel opening and reacts with the nitrogen to form an improved metal nitride surfaced barrier layer. A conductor core fills the opening over the barrier layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.