Path dependent power modeling
US6480815B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 1999 |
| Grant date | Nov 12, 2002 |
| Priority date | — |
| Expiry date | May 10, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for modeling the power consumed by a logic cell in a computer controlled power estimation process estimating the power consumed for an integrated circuit represented by logic cells and connections between cells. The present invention models power consumption within a logic cell associated with a particular designated pin (output, internal, or bidirectional) based on which input (or internal or bidirectional) pin transitioned causing the designated pin to transition. This is referred to as path dependent power modeling. A different power consumption value can be provided for each different modeled transition. The logic cells and the power consumption model for them are stored in a logic cell “library” within the computer system. Path dependent power modeling of the present invention allows library designers to specify a different set of power values depending on which pin transition (e.g., input pin) caused the designated pin to transition. Specifically, library designers are allowed to specify multiple internal power tables for each output with different “related_pins” fields. To take advantage of the path dependent power modeling, librar…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.