Double planar gated SOI MOSFET structure

US6483156B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• James W. Adkisson · Jericho, US
• John A. Bracchitta · South Burlington, US
• John J. Ellis-Monaghan · Grand Isle, US
• Jerome B. Lasky · South Burlington, US
• Effendi Leobandung · Stormville, US
• Kirk D. Peterson · Jericho, US
• Jed H. Rankin · South Burlington, US

Key dates

• Filing date: Mar 16, 2000
• Grant date: Nov 19, 2002
• Expiry date: Mar 16, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76283
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by an STI-like mandrel process. The double gated SOI MOSFET increases current drive per layout width and provides low out conductance.