Semiconductor contact and method of forming the same

US6486505B1 · kind B1 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Thomas Rupp · Stormville, US
• Jeffrey P. Gambino · Gresham, US
• Peter D. Hoh · Hopewell Junction, US
• Senthil Srinivasan · Wappingers Falls, US

Key dates

• Filing date: Mar 24, 2000
• Grant date: Nov 26, 2002
• Expiry date: Mar 24, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/05

Abstract

In one aspect, the present invention discloses a transistor device (see e.g., FIG. 3) that includes first and second source/drain regions 124a and 126 disposed in a semiconductor body 122 and separated by a channel region 128a. A dielectric layer 134a overlies the channel region 128a and a gate electrode 130a/132a overlies the dielectric layer 134a. In the preferred embodiment, the gate electrode includes a polysilicon layer 130a that extends a first lateral distance over the dielectric layer and a silicide layer 132a that extends a second lateral distance over the first polysilicon layer. In this example, the first lateral distance is greater than the second lateral distance.