Integrated memory having memory cells and reference cells, and operating method for such a memory
US6487128B2 · kind B2 · utility
2Cited by
4References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 24, 2001 |
| Grant date | Nov 26, 2002 |
| Priority date | — |
| Expiry date | Sep 24, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The memory has identically constructed memory cells and reference cells. An item of reference information is written into the reference cells by uncoupling the reference cells from the read amplifiers via first switching elements, and by electrically connecting the part of the bit lines that is connected to the reference cells via second switching elements to a potential line carrying the reference information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.