Selectively thin silicon film for creating fully and partially depleted SOI on same wafer
US6492209B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2000 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | Jan 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
Abstract
A method for providing partially depleted and fully depleted transistor devices on the same semiconductor wafer. At least one trench is etched into a bulk semiconductor wafer. The wafer is then filled with an insulating material and polished down to the surface level of the semiconductor wafer to form a generally planar surface. A handle wafer is provided having a substrate layer and an insulating layer. The planar surface of the semiconductor wafer is bonded to the insulating layer of the handle wafer. The trench filled regions of the semiconductor wafer form regions of a first thickness and the remaining regions of the semiconductor wafer form regions of a second thickness. Fully depleted transistor device can then be formed in the regions of the first thickness and partially depleted transistor devices can be formed in regions of the second thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.