Method for fully self-aligned FET technology

US6492210B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Karsten Wieczorek · Dresden, DE
• Manfred Horstmann · Dresden, DE
• Rolf Stephan · Dresden, DE
• Michael Raab · Salem, DE

Key dates

• Filing date: Mar 16, 2001
• Grant date: Dec 10, 2002
• Expiry date: Mar 16, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017

Abstract

This invention provides methods of forming a field-effect transistor in an integrated circuit using self-aligning technology on the basis of a gate electrode and sidewall spacer masking procedure both for forming the device isolation features and the source and drain regions. This invention enables an increase of the integration-density of semiconductor devices, a minimization of the parasitic capacitances in field-effect transistor devices, and a quicker manufacturing process.