DRAM access transistor
US6498062B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2001 |
| Grant date | Dec 24, 2002 |
| Priority date | — |
| Expiry date | Apr 27, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/608
Abstract
A method of forming memory devices, such as DRAM access transistors, having recessed gate structures is disclose. Field oxide areas for isolation are first formed over a semiconductor substrate subsequent to which transistor grooves are patterned and etched in a silicon nitride layer. The field oxide areas adjacent to the transistor grooves are then recessed, so that subsequently deposited polysilicon for gate structure formation can be polished relative to the adjacent and elevated silicon nitride.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.