Semiconductor package structure having central leads and method for packaging the same
US6501187B1 · kind B1 · utility
Inventors
Key dates
| Filing date | Nov 21, 2001 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | Nov 21, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package structure having central leads according to the invention includes a substrate, a semiconductor device, a plurality of wires, and glue. A long slot penetrating through the substrate is formed in the substrate. A plurality of bonding pads formed on the semiconductor device are mounted on substrate. The plurality of bonding pads on the semiconductor device are exposed via the long slot of the substrate. The length of the semiconductor device is smaller than that of the long slot of the substrate so that a channel is formed at one side of the long slot when the semiconductor device is mounted on the substrate. The plurality of wires are arranged within the long slot of the substrate for electrically connecting the plurality of bonding pads on the semiconductor device to the plurality of signal output terminals on the substrate. The glue is provided for sealing the upper surface of the substrate to protect the semiconductor device. The glue is poured into the long slot of the substrate via the channel formed by the long slot of the substrate, for covering the plurality of wires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.